OS IDLE Audit Details OMAPCONF (rev v1.74-1-g40ab0a2 built Mon 13 Jul 2020 12:48:16 PM CEST) HW Platform: Generic OMAP4 (Flattened Device Tree) OMAP4430 ES2.3 HS Device (HIGH performance (1.2GHz)) DIE ID: 01200026-00000001-0A3EBEDF-0C015016 UNKNOWN POWER IC UNKNOWN AUDIO IC SW Build Details: Build: Version: Devuan GNU/Linux 3 Kernel: Version: 5.8.0 Author: pbuilder@devuan-maemo-build-armv7 Toolchain: gcc (Debian 8.3.0-6) 8.3.0, GNU ld (GNU Binutils for Debian) 2.31. Type: #1 SMP PREEMPT Date: Tue Aug 25 09:33:57 UTC 2020 |-------------------------------------------------------------------------------------------------------| | CLOCK SPEED AUDIT | | | Clock Rate (MHz) | | | Module | Source Clock | OPP | Current | Expected | STATUS | |-------------------------------------------------------------------------------------------------------| | L4WKUP | WKUP_L4_ICLK2 | OPP100 | 26.000 | 38.400 | FAIL | | CONTROL_GEN_WKUP | WKUP_L4_ICLK2 | OPP100 | 26.000 | 38.400 | FAIL | | CONTROL_PADCONF_WKUP | WKUP_L4_ICLK2 | OPP100 | 26.000 | 38.400 | FAIL | | GPIO1 | WKUP_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | TIMER1 | GPT1_FCLK | OPP100 | 0.032768 | 0.032768 | pass | | WDT2 | WKUP_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | SYNCTIMER | FUNC_32K_CLK | OPP100 | 0.032768 | 0.032768 | pass | | SARRAM | L4_ICLK2 | OPP100 | 100.000 | 100.000 | pass | | KEYBOARD | WKUP_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | DEBUGSS | CORE_DPLL_EMU_CLK | OPP100 | 266.667 | 266.667 | pass | | MPU | MPU_DPLL_CLK | OPP100 | 600.000 | 600.000 | pass | | AESS | AESS_FCLK | OPP100 | 196.608 | 196.608 | pass | | DMIC | DMIC_ABE_FCLK | OPP100 | 24.576 | 24.576 | pass | | L4_ABE | ABE_ICLK2 | OPP100 | 98.304 | 98.304 | pass | | MCASP | MCASP1_FCLK | OPP100 | 24.576 | 24.576 | pass | | MCBSP1 | MCBSP1_FCLK | OPP100 | 24.576 | 24.576 | pass | | MCBSP2 | MCBSP2_FCLK | OPP100 | 24.576 | 24.576 | pass | | MCBSP3 | MCBSP3_FCLK | OPP100 | 24.576 | 24.576 | pass | | MCPDM | PAD_CLKS | OPP100 | 19.200 | 19.200 | pass | | SLIMBUS1 | SLIMBUS_UCLKS | OPP100 | 24.576 | 24.576 | pass | | TIMER5 | ABE_GPT5_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER6 | ABE_GPT6_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER7 | ABE_GPT7_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER8 | ABE_GPT8_FCLK | OPP100 | 0.032768 | 38.400 | warn. (3) | | WDT3 | ABE_ALWON_32K_CLK | OPP100 | 0.032768 | 0.032768 | pass | | IVAHD | IVAHD_ROOT_CLK | OPP100 | 266.053 | 266.057 | warn. (3) | | DSP | DSP_ROOT_CLK | OPP100 | 465.593 | 465.600 | warn. (3) | | SMARTREFLEX_CORE | SR_CORE_SYS_CLK | OPP100 | 26.000 | 38.400 | warn. (3) | | SMARTREFLEX_MPU | SR_MPU_SYS_CLK | OPP100 | 26.000 | 38.400 | warn. (3) | | SMARTREFLEX_IVA | SR_IVA_SYS_CLK | OPP100 | 26.000 | 38.400 | warn. (3) | | L4_CFG | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | CONTROL_GEN_CORE | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | CONTROL_PADCONF_CORE | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | SPINLOCK | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | SYSTEM_MAILBOX | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | SAR_ROM | CFG_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | C2C | C2C_L3X2_ICLK | OPP100 | 200.000 | 200.000 | pass | | C2C_FW | C2C_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | ICR_MDM | C2C_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | ICR_MPU | C2C_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | SDMA | DMA_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | MPU_M3 | MPU_M3_CLK | OPP100 | 400.000 | 400.000 | pass | | L3_1 | L3_ICLK1 | OPP100 | 200.000 | 200.000 | pass | | L3_2 | L3_ICLK2 | OPP100 | 200.000 | 200.000 | pass | | GPMC | L3_ICLK2 | OPP100 | 200.000 | 200.000 | pass | | OCMC_RAM | L3_ICLK2 | OPP100 | 200.000 | 200.000 | pass | | L3_3 | L3_INSTR_GICLK | OPP100 | 200.000 | 200.000 | pass | | L3_INSTR | L3_INSTR_GICLK | OPP100 | 200.000 | 200.000 | pass | | OCP_WP1 | L3_INSTR_GICLK | OPP100 | 200.000 | 200.000 | pass | | DMM | EMIF_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | EMIF_FW | EMIF_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | EMIF1 | EMIF_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | EMIF2 | EMIF_L3_ICLK | OPP100 | 200.000 | 200.000 | pass | | STD_EFUSE | STD_EFUSE_SYS_CLK | OPP100 | 26.000 | 38.400 | FAIL | | ISS | ISS_CLK | OPP100 | 400.000 | 400.000 | pass | | FDIF | FDIF_FCLK | OPP100 | 128.000 | 128.000 | pass | | DISPC | DSS_FCLK | OPP100 | 170.667 | 170.667 | pass | | DSI1 | DSS_FCLK | OPP100 | 170.667 | 170.667 | pass | | DSI2 | DSS_FCLK | OPP100 | 170.667 | 170.667 | pass | | HDMI | HDMI_PHY_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | GFX | GFX_FCLK | OPP100 | 307.200 | 307.200 | pass | | HSI | HSI_FCLK | OPP100 | 192.000 | 96.000 | warn. (3) | | MMC1 | MMC1_FCLK | OPP100 | 96.000 | 96.000 | pass | | MMC2 | MMC2_FCLK | OPP100 | 96.000 | 96.000 | pass | | FSUSBHOST | INIT_48MC_FCLK | OPP100 | 48.000 | 48.000 | pass | | HSUSBOTG | OTG_60M_FCLK | OPP100 | 60.000 | 60.000 | pass | | USBPHY | INIT_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | HSUSBHOST | INIT_48MC_FCLK | OPP100 | 48.000 | 48.000 | pass | | USBTLL | INIT_60M_FCLK | OPP100 | 60.000 | 60.000 | pass | | L4_PER | L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | TIMER2 | GPT2_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER3 | GPT3_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER4 | GPT4_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER9 | GPT9_FCLK | OPP100 | 0.032768 | 38.400 | warn. (3) | | TIMER10 | GPT10_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | TIMER11 | GPT11_FCLK | OPP100 | 26.000 | 38.400 | warn. (3) | | GPIO2 | PER_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | GPIO3 | PER_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | GPIO4 | PER_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | GPIO5 | PER_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | GPIO6 | PER_32K_GFCLK | OPP100 | 0.032768 | 0.032768 | pass | | MCSPI1 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | MCSPI2 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | MCSPI3 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | MCSPI4 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | UART1 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | UART2 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | UART3 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | UART4 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | I2C1 | PER_96M_FCLK | OPP100 | 96.000 | 96.000 | pass | | I2C2 | PER_96M_FCLK | OPP100 | 96.000 | 96.000 | pass | | I2C3 | PER_96M_FCLK | OPP100 | 96.000 | 96.000 | pass | | I2C4 | PER_96M_FCLK | OPP100 | 96.000 | 96.000 | pass | | MMC3 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | MMC4 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | SLIMBUS2 | SLIMBUS_CORE_UCLKS | OPP100 | 24.576 | 24.576 | pass | | MMC5 | PER_48M_FCLK | OPP100 | 48.000 | 48.000 | pass | | ELM | PER_L4_ICLK | OPP100 | 100.000 | 100.000 | pass | | HDQ1W | 12M_FCLK | OPP100 | 12.000 | 12.000 | pass | | MCBSP4 | PER_MCBSP4_FCLK | OPP100 | 96.000 | 96.000 | pass | |-------------------------------------------------------------------------------------------------------| NB: (1) Internal error (data not found). (2) OPP not found, could not audit module rate. (3) Clock rate does no match target rate, but module is disabled (no power impact). (4) No target clock rate available (module not used on TI reference platform). FAILED! Clock Speed audit completed with 4 error and 16 warning. |-----------------------------------------------------------------------------------------------------------------| | Static Dependency AUDIT From | MPU | IVAHD | DSP | C2C | SDMA | MPU_M3 | CAM | DSS | GFX | L3INIT | L4SEC | |-----------------------------------------------------------------------------------------------------------------| | Towards | | | | | | | | | | | | | L4WKUP | Pass | | Pass | | Pass | Pass | | | | Pass | | | ABE | Pass | | Pass | Pass | Pass | Pass | | | | Pass | | | IVAHD | Pass | | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Pass | | | DSP | Pass | | | | | Pass | | | | | | | ALWONCORE | Ign. | | Ign. | | | Ign. | | | | | | | L4CFG | FAIL | | Pass | Pass | Pass | FAIL | | | | Pass | | | C2C | Ign. | | | | | | | | | | | | SDMA | Ign. | | | | | Ign. | | | | | | | MPU_M3 | Pass | | | | Pass | | | | | | | | L3_1 | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Ign. | Pass | Ign. | Pass | | L3_2 | Pass | Ign. | Pass | Pass | Ign. | Pass | Ign. | Pass | Ign. | Ign. | Ign. | | MEMIF | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Pass | Pass | | CUST_EFUSE | Ign. | | Ign. | | | Ign. | | | | | | | CAM | Ign. | | Ign. | | Ign. | Ign. | | | | | | | DSS | Pass | | | | Pass | Pass | | | | | | | GFX | Pass | | | | | Pass | | | | | | | L3INIT | Pass | | Pass | Pass | Pass | Pass | | | | | | | L4SEC | Pass | | | | Pass | Pass | | | | Pass | | | L4PER | FAIL | | Pass | Pass | Pass | FAIL | | | | Pass | Pass | |-----------------------------------------------------------------------------------------------------------------| NB: - ALL STATIC DEPENDENCIES expected to be DISABLED in FINAL product (except HW errata). - Pass = static dependency setting correct. - FAIL = static dependency setting incorrect. - Ign. = ignored as static dependency is Read-Only. - Empty cell = static dependency does not exist. FAILED! Static Dependency configuration audit completed with 4 error(s) and 0 warning(s). |--------------------------------------------------------------| | ABE Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | ON | RET | ON | | Logic | ON | OFF | | | Memory | | | | | PERIPHMEM | ON | OFF | | | AESSMEM | ON | RET | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | ABE Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | ABE_24M_FCLK | GATED | | ABE_ALWON_32K_CLK | RUNNING | | ABE_SYSCLK | GATED | | 24M_FCLK | GATED | | ABE_ICLK2 | GATED | | DPLL_ABE_X2_CLK | GATED | | PAD_CLKS | GATED | | SLIMBUS_CLK | GATED | | OPP Divider | ABE_CLK = DPLL_ABE_X2_CLK/1 | |--------------------------------------------------------------| |----------------------------------------------------------| | L4ABE Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | |----------------------------------------------------------| |----------------------------------------------------------| | AESS Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | AESS_FCLK | = ABE_CLK / 1 | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | AESSMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | PDM Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | DMIC Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 24MHz from DPLL_ABE | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCASP Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCBSP1 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 24MHz from DPLL_ABE | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCBSP2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 24MHz from DPLL_ABE | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCBSP3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 24MHz from DPLL_ABE | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | SLIMBUS Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | SLIMBUS | Disabled | | FCLK2 | Disabled | | FCLK1 | Disabled | | FCLK0 | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | PERIPHMEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | TIMER5 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | ABE_SYSCLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | TIMER6 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | ABE_SYSCLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | TIMER7 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | ABE_SYSCLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | TIMER8 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | ABE_ALWON_32K_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | WDT3 Module Configuration | |--------------------------------|-------------------------| | Mode | Enabled (EXPLICITLY) | | Idle Status | OCP-ONLY Idle | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | IVAHD Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | RET | RET | RET | | Logic | OFF | OFF | | | Memory | | | | | TCM2 | RET | RET | | | TCM1 | RET | RET | | | SL2 | RET | RET | | | HWA | OFF | OFF | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | IVAHD Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | IVAHD Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | HWA | LOST | | TCM2 | LOST | | TCM1 | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | SL2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Not in Standby | | Last Context | | | SL2 | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | GFX Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | OFF | OFF | | | Logic | OFF | | | | Memory | | | | | MEM | OFF | OFF | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | GFX Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | GFX_FCLK | GATED | | GFX_L3_ICLK | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | GFX Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | GFX_FCLK | = DPLL_PER | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | MEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | DSP Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | RET | RET | RET | | Logic | OFF | OFF | | | Memory | | | | | EDMA | RET | RET | | | L2$ | RET | RET | | | L1$ | RET | RET | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | DSP Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | DSP Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | EDMA | LOST | | L2$ | LOST | | L1$ | LOST | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | CAM Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | OFF | OFF | | | Logic | OFF | | | | Memory | | | | | MEM | OFF | OFF | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | CAM Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | SW-Forced Sleep | | Clock State | | | FDIF FCLK | GATED | | CAM PHY CTRL CLK | GATED | | ISS_ICLK | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | ISS Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | CAM_PHY_CTRL_GCLK 96Mhz | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | MEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | FDIF Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | FDIF_FCLK | = FUNC_128_CLK / 1 | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | MEM | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | L3INIT Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | RET | RET | RET | | Logic | ON | RET | | | Memory | | | | | L3INIT Bank1 | OFF | OFF | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | L3INIT Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | INIT_32K_FCLK | GATED | | INIT_60M_P2_FCLK | GATED | | INIT_60M_P1_FCLK | GATED | | HSIC_P2_FCLK | GATED | | HSIC_P1_FCLK | GATED | | UTMI_ROOT_24M_FCLK | GATED | | TLL_CH2_FCLK | GATED | | TLL_CH1_FCLK | GATED | | TLL_CH0_FCLK | GATED | | HSIC_P2_480M_FCLK | GATED | | HSIC_P1_480M_FCLK | GATED | | INIT_HSMMC2_FCLK | GATED | | INIT_HSMMC1_FCLK | GATED | | INIT_HSI_FCLK | GATED | | USB_DPLL_HS_CLK | GATED | | USB_DPLL_CLK | GATED | | INIT_48MC_FCLK | GATED | | INIT_48M_FCLK | GATED | | L4_INIT_ICLK | GATED | | L3_INIT_ICLK | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | MMC1 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 96MHz from DPLL_PER | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | L3INIT_BANK1 | LOST | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | MMC2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 96MHz from DPLL_PER | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | L3INIT_BANK1 | LOST | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | HSI Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 192MHz / 1 | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | L3INIT_BANK1 | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | HSUSBHOST Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | UTMI Port2 Source | internal | | UTMI Port1 Source | internal | | SAR MODE | Disabled | | Optional functional clock | | | FUNC48MCLK | Disabled | | HSIC480M_P2_CLK | Disabled | | HSIC480M_P1_CLK | Disabled | | HSIC60M_P2_CLK | Disabled | | HSIC60M_P1_CLK | Disabled | | UTMI_P3_CLK | Disabled | | UTMI_P2_CLK | Disabled | | UTMI_P1_CLK | Disabled | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | HSUSBOTG Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | 60MHz Source CLK | on die UTMI PHY | | Optional XCLK (60MHz) clock | Disabled | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | L3INIT_BANK1 | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | HSUSBTLL Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | SAR MODE | Disabled | | Optional functional clock | | | USB_CH2_CLK | Disabled | | USB_CH1_CLK | Disabled | | USB_CH0_CLK | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | P1500 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Standby Status | Standby | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | FSUSB Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | USBPHY Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | 32KHz clock | Disabled | | PHY_48M | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------| | MPU LPRM Configuration | CPU0 | CPU1 | |--------------------------------|-----------|-----------| | Current Power State | ON | ON | | Current Logic State | ON | ON | | Current L1$ State | ON | ON | | Standby Status | RUNNING | RUNNING | | | | | | Target Power State | ON | ON | | Logic State When Domain is RET | OFF | OFF | | Clock Control | HW-Auto | HW-Auto | | | | | | Last Power State | OFF | OFF | | Last L1$ Context | LOST | LOST | | Last CPU Context | LOST | LOST | |--------------------------------------------------------| |--------------------------------------------------------| | SCU Configuration | CPU0 | CPU1 | |--------------------------------|-----------|-----------| | CPU Power Status | Normal | Normal | |--------------------------------------------------------| |--------------------------------------------------------------| | MPU Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | ON | RET | RET | | Logic | ON | OFF | | | Memory | | | | | RAM | ON | RET | | | L2$ | ON | RET | | | L1$ | ON | RET | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | MPU Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | MPU Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RAM | RETAINED | | L2$ | RETAINED | | L1$ | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------| | MPU DPLL Configuration | |--------------------------------|-----------------------| | Status | Locked | | Clock Speed (MHz) | 600 | | Mode | Lock | | Low-Power Mode | Disabled | | Autoidle Mode | Auto LPST | | M2 Output Autogating | Enabled | |--------------------------------------------------------| NB: type "omapconf dplls cfg" for detailed DPLL configuration. |--------------------------------------------------------------| | DSS Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | RET | RET | | | Logic | OFF | OFF | | | Memory | | | | | MEM | OFF | OFF | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | DSS Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | HDMI PHY 48MHz FCLK | GATED | | DSS ALWON SYSCLK | GATED | | DSS_FCLK | GATED | | DSS_L3_ICLK | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | DSS Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | TV | Disabled | | SYS | Disabled | | 48MHz | Disabled | | DSS | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | MEM | LOST | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | L4_PER Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | ON | RET | ON | | Logic | ON | OFF | | | Memory | | | | | NONRETAINED | ON | OFF | | | RETAINED | ON | RET | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | L4_PER Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | PER_ABE_24M_FCLK | GATED | | PER_SYS_FCLK | GATED | | PER_MCBSP4_FCLK | GATED | | PER_96M_FCLK | RUNNING | | PER_48M_FCLK | RUNNING | | PER_32K_FCLK | GATED | | PER_24MC_FCLK | GATED | | FUNC_12M_FCLK | GATED | | DMT9_FCLK | GATED | | DMT4_FCLK | GATED | | DMT3_FCLK | GATED | | DMT2_FCLK | GATED | | DMT11_FCLK | GATED | | DMT10_FCLK | GATED | | L4_PER_GICLK | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | L4_PER Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | SYS_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | SYS_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | SYS_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER9 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | 32KHz | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER10 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | SYS_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPTIMER11 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | SYS_CLK | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | ELM Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPIO2 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Optional functional clock | Disabled | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | GPIO3 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Optional functional clock | Disabled | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | GPIO4 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Optional functional clock | Disabled | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | GPIO5 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Optional functional clock | Disabled | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | GPIO6 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Optional functional clock | Disabled | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | HDQ1W Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | I2C1 Module Configuration | |--------------------------------|-------------------------| | Mode | Enabled (EXPLICITLY) | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | I2C2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | I2C3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | I2C4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCBSP4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | FCLK Source | DPLL_PER 96MHz | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | NONRETAINED_BANK | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCSPI1 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCSPI2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCSPI3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MCSPI4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MMCSD3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | NONRETAINED_BANK | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MMCSD4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | NONRETAINED_BANK | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MMCSD5 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | NONRETAINED_BANK | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | SLIMBUS2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Optional functional clock | | | SLIMBUS | Disabled | | PER_ABE_24M_FCLK | Disabled | | PER_24MC_FCLK | Disabled | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | NONRETAINED_BANK | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | UART1 Module Configuration | |--------------------------------|-------------------------| | Mode | Enabled (EXPLICITLY) | | Idle Status | In Transition | | Last Context | | | RETAINED_BANK | RETAINED | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | UART2 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | RETAINED_BANK | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | UART3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | RETAINED_BANK | RETAINED | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | UART4 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | RETAINED_BANK | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | CORE Power Domain Configuration | |--------------------------------------------------------------| | Power State | Current | Target | Last | |--------------------------------|---------|---------|---------| | Domain | ON | RET | ON | | Logic | ON | OFF | | | Memory | | | | | OCP_WP Bank & DMM Bank2 | ON | OFF | | | MPU_M3 Unicache | ON | RET | | | MPU_M3 L2 RAM | ON | RET | | | OCM RAM | ON | RET | | | DMA/ICR Bank & DMM Bank1 | ON | RET | | |--------------------------------------------------------------| | Ongoing Power Transition? | NO | |--------------------------------------------------------------| |--------------------------------------------------------------| | L3_1 Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | L3_1 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | L3_2 Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | L3_2 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | GPMC Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | |----------------------------------------------------------| |----------------------------------------------------------| | OCMC_RAM Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | OCM RAM | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | MPU_M3 Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | MPU_M3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Standby Status | Standby | | Last Context | | | L2RAM | LOST | | Unicache | LOST | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | SDMA Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | SDMA Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Standby Status | Standby | | Last Context | | | CORE_OTHER_BANK | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | MEMIF Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | PHY_ROOT_CLK | RUNNING | | DLL_CLK | RUNNING | | L3_EMIF_ICLK | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | DMM Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | CORE_NRET_BANK | LOST | | CORE_OTHER_BANK | RETAINED | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | EMIF_FW Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | EMIF_1 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | EMIF_2 Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | DLL Module Configuration | |--------------------------------|-------------------------| | Optional DLL_CLK FCLK | Disabled | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | C2C Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | | | C2C_L3X2_ICLK | GATED | | L4_C2C_ICLK | GATED | | L3_C2C_ICLK | GATED | |--------------------------------------------------------------| |----------------------------------------------------------| | C2C Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Standby Status | Standby | | Last Context | | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MODEM_ICR Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Last Context | | | CORE_OTHER_BANK | LOST | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | C2C_FW Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | OCP-ONLY Idle | | Last Context | | | RFF-Based | LOST | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | L4CFG Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | L4_CFG Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | HW_SEM Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | MAILBOX Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | RFF-Based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | SAR_ROM Module Configuration | |--------------------------------|-------------------------| | Mode | HW-Auto | | Idle Status | Full ON | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |--------------------------------------------------------------| | L3INSTR Clock Domain Configuration | |--------------------------------|-----------------------------| | Clock State Transition control | HW-Auto | | Clock State | RUNNING | |--------------------------------------------------------------| |----------------------------------------------------------| | L3_3 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | L3_INSTR Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------| | OCP_WP1 Module Configuration | |--------------------------------|-------------------------| | Mode | Disabled (NO ACCESS) | | Idle Status | Disabled (NO ACCESS) | | Last Context | | | CORE_NRET_BANK | LOST | | RFF-Based | RETAINED | | DFF-based | LOST | |----------------------------------------------------------| |----------------------------------------------------------------------------------------------------| | MODULES SYSCONFIG AUDIT | AUTOIDLE | IDLE | STANDBY | CLOCKACTIVITY | |----------------------------------------------------------------------------------------------------| | CONTROL_GEN_WKUP | | Pass | | | | CONTROL_PADCONF_WKUP | | Pass | | | | GPIO1 | Pass | Pass | | | | TIMER1 | Pass | Warning (No Idle) | | Warning (F-CLK ON / I-CLK AUTO) | | WDT2 | | Pass | | | | SYNCTIMER | | Pass | | | | KEYBOARD | Pass | Pass | | Pass | | AESS | NA | NA | NA | NA | | DMIC | NA | NA | NA | NA | | MCASP | NA | NA | NA | NA | | MCBSP1 | NA | NA | NA | NA | | MCBSP2 | NA | NA | NA | NA | | MCBSP3 | NA | NA | NA | NA | | MCPDM | NA | NA | NA | NA | | SLIMBUS1 | NA | NA | NA | NA | | TIMER5 | NA | NA | NA | NA | | TIMER6 | NA | NA | NA | NA | | TIMER7 | NA | NA | NA | NA | | TIMER8 | NA | NA | NA | NA | | WDT3 | | Pass | | | | IVAHD | NA | NA | NA | NA | | DSP | NA | NA | NA | NA | | MMU_DSP | NA | NA | NA | NA | | DSP_WUGEN | NA | NA | NA | NA | | SMARTREFLEX_CORE | NA | NA | NA | NA | | SMARTREFLEX_MPU | NA | NA | NA | NA | | SMARTREFLEX_IVA | NA | NA | NA | NA | | CONTROL_GEN_CORE | | Pass | | | | CONTROL_PADCONF_CORE | | Pass | | | | SPINLOCK | Pass | Pass | | Pass | | SYSTEM_MAILBOX | | Pass | | | | ICR_MDM | Pass | Pass | | | | ICR_MPU | Pass | Pass | | | | SDMA | NA | NA | NA | NA | | GPMC | Pass | Pass | | | | DMM | | Pass | | | | ISS | NA | NA | NA | NA | | CCP2 | NA | NA | NA | NA | | CSI2_A | NA | NA | NA | NA | | CSI2_B | NA | NA | NA | NA | | TCTRL | NA | NA | NA | NA | | BTE | NA | NA | NA | NA | | CBUFF | NA | NA | NA | NA | | ISP5 | NA | NA | NA | NA | | RSZ | NA | NA | NA | NA | | FDIF | NA | NA | NA | NA | | GFX | NA | NA | NA | NA | | HSI | NA | NA | NA | NA | | MMC1 | NA | NA | NA | NA | | MMC1_HL | NA | NA | NA | NA | | MMC2 | NA | NA | NA | NA | | MMC2_HL | NA | NA | NA | NA | | UNIPRO_1 | NA | NA | NA | NA | | FSUSBHOST | NA | NA | NA | NA | | HSUSBOTG | NA | NA | NA | NA | | HSUSBHOST | NA | NA | NA | NA | | USBTLL | NA | NA | NA | NA | | TIMER2 | NA | NA | NA | NA | | TIMER3 | NA | NA | NA | NA | | TIMER4 | NA | NA | NA | NA | | TIMER9 | NA | NA | NA | NA | | TIMER10 | NA | NA | NA | NA | | TIMER11 | NA | NA | NA | NA | | GPIO2 | NA | NA | NA | NA | | GPIO3 | NA | NA | NA | NA | | GPIO4 | NA | NA | NA | NA | | GPIO5 | NA | NA | NA | NA | | GPIO6 | NA | NA | NA | NA | | MCSPI1_HL | NA | NA | NA | NA | | MCSPI1 | NA | NA | NA | NA | | MCSPI2_HL | NA | NA | NA | NA | | MCSPI2 | NA | NA | NA | NA | | MCSPI3_HL | NA | NA | NA | NA | | MCSPI3 | NA | NA | NA | NA | | MCSPI4_HL | NA | NA | NA | NA | | MCSPI4 | NA | NA | NA | NA | | UART1 | Pass | Pass | | | | UART2 | NA | NA | NA | NA | | UART3 | NA | NA | NA | NA | | UART4 | NA | NA | NA | NA | | I2C1 | Pass | Pass | | Warning (F-CLK ON / I-CLK AUTO) | | I2C2 | NA | NA | NA | NA | | I2C3 | NA | NA | NA | NA | | I2C4 | NA | NA | NA | NA | | MMC3 | NA | NA | NA | NA | | MMC3_HL | NA | NA | NA | NA | | MMC4 | NA | NA | NA | NA | | MMC4_HL | NA | NA | NA | NA | | SLIMBUS2 | NA | NA | NA | NA | | MMC5 | NA | NA | NA | NA | | MMC5_HL | NA | NA | NA | NA | | ELM | NA | NA | NA | NA | | HDQ1W | NA | NA | NA | NA | | MCBSP4 | NA | NA | NA | NA | |----------------------------------------------------------------------------------------------------| NB: - Show 'NA' when module is disabled. - Show empty cell(s) when module does not feature this mode. - AUTOIDLE MODE: - Report Pass if enabled, FAIL otherwise. - IDLE MODE: - Report Pass if set to "Smart-Idle" or "Smart-Idle Wakeup" (when available). - Modules featuring "Smart-Idle Wakeup" mode must be programmed in this mode. Audit will report FAIL even with "Smart-Idle" mode. - Report Warning (with setting) in case of "Force-Idle" mode. - Report FAIL (with incorrect setting) otherwise. - STANDBY MODE: - Report Pass if set to "Smart-Standby" or "Smart-Standby Wakeup" (when available). - Modules featuring "Smart-Standby Wakeup" mode must be programmed in this mode. Audit will report FAIL even with "Smart-Standby" mode. - Report Warning (with setting) in case of "Force-Standby" mode. - Report FAIL (with incorrect setting) otherwise. - CLOCKACTIVITY MODE: - Report Pass if both I-CLK and F-CLK are set to AUTO mode. - Report Warning if one of I-CLK or F-CLK is set to ON mode. - Report FAIL (with incorrect setting) otherwise. SUCCESS! Modules SYSCONFIG registers audit completed with 0 error (3 warning(s)) |----------------------------------------------------------------------------------------------------------| | DPLL Configuration | DPLL_MPU | DPLL_IVA | DPLL_CORE | DPLL_PER | DPLL_ABE | DPLL_USB | |----------------------------------------------------------------------------------------------------------| | Status | Locked | Stopped | Locked | Locked | Stopped | Stopped | | | | | | | | | | Mode | Lock | Lock | Lock | Lock | Lock | Lock | | Automatic Control | Auto LPST | Auto LPST | Auto LPST | Auto LPST | Auto LPST | Auto LPST | | LPST = Low-Power STop | | | | | | | | FRST = Fast-Relock STop | | | | | | | | LPBP = Low-Power ByPass | | | | | | | | FRBP = Fast-Relock ByPass | | | | | | | | MNBP = MN ByPass | | | | | | | | Low-Power Mode | Disabled | Disabled | Disabled | Disabled | Enabled | Disabled | | | | | | | | | | Automatic Recalibration | Disabled | Disabled | Disabled | Disabled | Disabled | Disabled | | Clock Ramping during Relock | Disabled | Disabled | Disabled | Disabled | Disabled | Disabled | | Ramping Rate (x REFCLK(s)) | 2 | 2 | 2 | 2 | 2 | 2 | | Ramping Levels | 4,2,1.5 | No Ramp | 8,4,2 | No Ramp | No Ramp | No Ramp | | | | | | | | | | Bypass Clock | CLKINPULOW | CLKINP | CLKINP | CLKINP | CLKINPULOW | CLKINP | | Bypass Clock Divider | 1 | 2 | | | | | | REGM4XEN Mode | Disabled | Disabled | Disabled | Disabled | Enabled | Disabled | | | | | | | | | | M Multiplier Factor | 300 | 967 | 400 | 384 | 750 | 480 | | N Divider Factor | 12 | 26 | 12 | 12 | 0 | 12 | | Lock Frequency (MHz) | 1200 | 0 (1862) | 1600 | 1536 | 0 (196) | 0 (960) | | | | | | | | | | M2 Output | | | | | | | | Status | Enabled | | Enabled | Gated | Gated | Gated | | Clock Divider | 1 (x2) | | 1 (x2) | 8 (x2) | 1 (x2) | 2 (x2) | | Clock Speed (MHz) | 600 | | 800 | 96 | 0 (98) | 0 (480) | | Autogating | Enabled | | Enabled | Enabled | Enabled | Enabled | | | | | | | | | | X2_M2 Output | | | | | | | | Status | | | Gated | Enabled | Gated | Gated | | Clock Divider | | | 1 | 8 | 1 | 2 | | Clock Speed (MHz) | | | 1600 | 192 | 0 (196) | 0 (960) | | Autogating | | | Enabled | Enabled | Enabled | Enabled | | | | | | | | | | X2_M3 Output | | | | | | | | Status | | | Gated | Gated | Gated | | | Clock Divider | | | 5 | 6 | 1 | | | Clock Speed (MHz) | | | 320 | 256 | 0 (196) | | | Autogating | | | Enabled | Enabled | Enabled | | | | | | | | | | | X2_M4 Output | | | | | | | | Status | | Gated | Enabled | Gated | | | | Clock Divider | | 4 | 8 | 12 | | | | Clock Speed (MHz) | | 0 (465) | 200 | 128 | | | | Autogating | | Enabled | Enabled | Enabled | | | | Auto Power Down | | Disabled | Disabled | Disabled | | | | | | | | | | | | X2_M5 Output | | | | | | | | Status | | Gated | Enabled | Gated | | | | Clock Divider | | 7 | 4 | 9 | | | | Clock Speed (MHz) | | 0 (266) | 400 | 170 | | | | Autogating | | Enabled | Enabled | Enabled | | | | Auto Power Down | | Disabled | Disabled | Disabled | | | | | | | | | | | | X2_M6 Output | | | | | | | | Status | | | Gated | Gated | | | | Clock Divider | | | 6 | 4 | | | | Clock Speed (MHz) | | | 266 | 384 | | | | Autogating | | | Enabled | Enabled | | | | Auto Power Down | | | Disabled | Disabled | | | | | | | | | | | | X2_M7 Output | | | | | | | | Status | | | Gated | Gated | | | | Clock Divider | | | 6 | 5 | | | | Clock Speed (MHz) | | | 266 | 307 | | | | Autogating | | | Enabled | Enabled | | | | Auto Power Down | | | Disabled | Disabled | | | |----------------------------------------------------------------------------------------------------------| |---------------------------------------------------------------------------| | OS IDLE Power Settings Audit | Current | Expected (POR) | STATUS | |---------------------------------------------------------------------------| | CPUFreq Governor | ondemand | Not found | Warning | | | | | | | OPPs | | | | | VDD_MPU | OPP100 | UNKNOWN | Warning | | VDD_IVA | OPP100 | UNKNOWN | Warning | | VDD_CORE | OPP100 | UNKNOWN | Warning | | | | | | | Smart-Reflex | | | | | MPU | | | Ignored (3) | | IVA | | | Ignored (3) | | CORE | | | Ignored (3) | | | | | | | Voltages | | | | | VDD_MPU | NA | <= 0.000000 V | Warning | | VDD_IVA | NA | <= 0.000000 V | Warning | | VDD_CORE | NA | <= 0.000000 V | Warning | | | | | | | RETENTION Voltages | | | | | VDD_MPU | -0.000008 V | 0.759640 V | Warning | | VDD_IVA | -0.000008 V | 0.759640 V | Warning | | VDD_CORE | -0.000008 V | 0.759640 V | Warning | | | | | | | Clock Speeds (4) | | | FAIL | | | | | | | Static Dependencies (4) | | | FAIL | | | | | | | CPU1 Power State | ON | FIXME | Warning | | | | | | | Lowest C-State entered | C0 | C0 | Warning | | | | | | | Power & | | | | | Clock Domains State (2) | | | | | ABE | ON | OFF | FAIL | | ABE | Running | Gated | FAIL | | IVAHD | RET | OFF | FAIL | | IVAHD | Gated | Gated | Pass | | GFX | OFF | OFF | Pass | | GFX | Gated | Gated | Pass | | DSP | RET | OFF | FAIL | | DSP | Gated | Gated | Pass | | CAM | OFF | OFF | Pass | | CAM | Gated | Gated | Pass | | L3_INIT | RET | ON | Ignored (2) | | L3_INIT | Gated | Running | Ignored (2) | | MPU | ON | ON | Ignored (1) | | MPU | Running | Running | Ignored (1) | | DSS | RET | OFF | FAIL | | DSS | Gated | Gated | Pass | | L4_PER | ON | OFF | Ignored (1) | | L4_PER | Running | Gated | Ignored (1) | | L4_SEC | Gated | Gated | Pass | | CORE | ON | ON | Ignored (1) | | EMIF | Running | Running | Ignored (1) | | L3_1 | Running | Running | Ignored (1) | | L4_CFG | Running | Gated | Ignored (1) | | MPU_M3 | Gated | Gated | Pass | | DMA | Gated | Gated | Pass | | L3_2 | Running | Gated | Ignored (1) | | L3_INSTR | Running | Gated | Ignored (1) | | C2C | Gated | Gated | Pass | | | | | | | SYSCONFIG Settings (4) | | | Warning | | | | | | | DPLLs Status (4) | | | | | ABE | Stopped | Bypassed | Warning | | CORE | Locked | Bypassed | Warning | | PER | Locked | Bypassed | Warning | | MPU | Locked | Bypassed | Warning | | IVA | Stopped | Bypassed | Warning | | USB | Stopped | Bypassed | Warning | |---------------------------------------------------------------------------| Notes: (1) Cannot be tested due to OMAPCONF execution that falses the result. (2) Due to auto-gating/auto-idle, item may be either gated/idle or running at the time status is read. (3) Cannot be tested due to disabled sensors in SR class 1.5 (outside of periodic recalibration). (4) For full audit details, use "full_log" and check "./os_idle_uc_audit_details.txt" file. |---------------------------------------------------------------| | OS IDLE Audit Metrics | Count | Breakout (%) | |---------------------------------------------------------------| | Number of tests run | 52 | 100% | | Number of tests passed | 26 | 50.00% | | Number of tests passed with warning(s) | 19 | 36.54% | | Number of tests failed | 7 | 13.46% | |---------------------------------------------------------------| OS IDLE Use-Case Audit summary saved in "./os_idle_uc_audit_summary.txt" file. OS IDLE Use-Case Audit details saved in "./os_idle_uc_audit_details.txt" file. FAILED! OS IDLE Use-Case Power Settings Audit completed with 7 error(s) and 19 warning(s).